Wafer stacking refers to the process of adhering a device wafer (a silicon wafer with a device, or a device layer which is to form a layer of a multi-layer device) to a carrier wafer. An assembly of a processed wafer (with devices) glued to a carrier wafer used to support the processed wafer while it is manipulated is referred to as a stacked wafer. The carrier wafer is used only for handling purposes, and is removed and discarded after the device wafer is processed. Stacked wafers are commonly assembled and used during the manufacture of processed wafers incorporating “thru silicon vias” into their design. Thru silicon vias (TSV's) are metal (often Cu) wires embedded in the device wafer that allow connection to other device wafers, so that several device wafers may be stacked, one on top of the other. The device wafer will eventually be substantially thinned—typically thinned to less than 100 um during grinding and polishing to expose the TSV's. Because it is very thing, the device wafer must be supported by a carrier wafer to avoid damaging or destroying it during grinding and polishing needed to expose the TSV's. The carrier wafer is glued to the device wafer, and provides substantial support for the device wafer.
Through silicon vias are formed by etching blind holes in silicon, coating the holes with silicon oxide, and filling those holes with copper. A device layer is then built up over the copper filled TSV's. The copper TSV's are thus buried deep in the device wafer, and must be uncovered so that they can be connected, eventually, to another device wafer. The TSV's are uncovered by grinding and polishing. The bulk of the silicon covering the TSV's is quickly removed by grinding, until most of the silicon is removed and the TSV's are covered only by a very thin layer of remaining silicon. This layer is not removed by grinding so as to avoid smearing copper over the silicon, which would contaminate the silicon. To expose the vias, the remaining thin layer of silicon is removed by etching or polishing, so that the vias protrude slightly (a few microns) from the silicon layer. Then an additional layer of silicon oxide is deposited on the wafer, covering the entire wafer surface and the exposed vias. Next, an additional polishing step is used to remove the silicon oxide from the via tips without removing the silicon oxide from the remaining silicon. The silicon oxide prevents any copper smear from contaminating the silicon of the device wafer. In this condition, the device wafer may be stacked together with additional device wafers to create an integrated circuit with several layers of devices.
The device wafer and TSV's should be as flat as possible to allow the most compact stacking, and avoid defects in a final assembly of several wafers. However, the several surfaces of the device wafer, carrier wafer, and the glue used to join them together are not perfectly flat. When the stacked wafer is drawn onto the chuck, with the carrier wafer in contact with the chuck, the contacting surface of the carrier wafer is pulled perfectly flat. The overlying layers are thus deformed by any unevenness or dis-uniformities in the flatness or run out, such that the back surface of the device wafer is not flat, and conforms to any bumps and unevenness in the carrier wafer, adhesive layer, and device layer. Thus, the tips of the copper TSV's are not all the same height, and thus an excess of device wafer silicon must be left on the device wafer in the grinding step to avoid smearing. This also leads to inconsistent Remaining Silicon Thickness.